The present invention relates to serial data communication receivers for data capture and clock recovery and, more particularly, to a receivers and method for equalizing a serial data signal.
Serial communication receivers are used in integrated circuits, such as application specific integrated circuits (ASICs), for clock synchronization and for recovery of serial data streams from transmission channels. Clock signals and data are recovered by detecting transitions in the serial data stream and the valid data between those transitions. The time and voltage ranges over which the data is valid within each cycle in the stream is known as the data xe2x80x9ceyexe2x80x9d. In order to minimize bit errors in the recovered data, the serial data stream is preferably sampled near the center of this eye. However, the limited-bandwidth nature of a transmission channel results in distortion and closure of the data eye in both the time and voltage domains.
One current method of limiting distortion and closure of the data eye at the receiver is to provide fixed equalization of the incoming data signal through a high-pass filter, or equalizer, which is located either on-board or on-chip. The equalizer boosts the voltage sensitivity of the receiver at those frequencies at which attenuation of the incoming data signal due to the frequency response of the transmit media rolls off. The net effect is an extension in the flat region of the frequency response of the combination of the transmitter, the transmit media and the receiver. However, the frequency response of the transmit media can vary with each application. Therefore, the fixed frequency response of the equalizer may not be optimal for a particular application.
A serial data communication receiver is desired that is capable of evaluating the performance of a complete transceiver system, which includes the transmit media, and adjusting the frequency response of the receiver to compensate for this performance and essentially open the eye of the incoming data stream.
One aspect of the present invention is directed to a method of adaptively equalizing a serial data signal. The method includes equalizing the serial data signal with first and second equalizers to produce first and second equalized serial data signals. The first and second equalized serial data signals are then de-serialized to produce first and second recovered data signals. A frequency response of the second equalizer is varied over a range of frequency response settings during the steps of equalizing and de-serializing. A data eye size of the second equalized serial data signal is measured for each of the frequency response settings, and a frequency response of at least one of the first and second equalizers is set to one of the frequency response settings based on the measured data eye sizes.
Another aspect of the present invention relates to a serial data communication receiver, which includes a serial data input. First and second equalizers are coupled to the serial data input and each have a frequency response, which is variable over a range of frequency response settings based on a frequency response control input. First and second capture latch circuits are coupled to the first and second equalizers, respectively, in a phase-locked loop and have first and second recovered data outputs, respectively. A comparator is coupled to the first and second recovered data outputs and has an error output. A frequency response control feedback circuit is coupled between the error output and the frequency response control input of at least one of the first and second equalizers and adjusts the frequency response of that equalizer based the error output.
Yet another aspect of the present invention relates to a serial data communication receiver, which includes a serial data input, first and second equalizers, first and second capture latch circuits, and an equalization control circuit. The first and second equalizers are coupled to the serial data input and have first and second equalized serial data outputs, respectively. Each equalizer has a frequency response that is variable over a range of frequency response settings. The first and second capture latch circuits are coupled to the first and second equalized serial data outputs, respectively, in a phase-locked loop and have first and second recovered data outputs, respectively. The equalization control circuit measures a data eye size of the second equalized serial data output over the range of frequency response settings of the second equalizer and sets the frequency response of at least one of the first and second equalizers to one of the frequency response settings based on the measured data eye sizes.